Static Timing Analysis

Project : geiger
Build Time : 08/20/17 10:34:20
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 5.00
VDDD : 5.00
Voltage : 5
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+ Timing Violation Section
Note: If your design will only ever run at typical room temperatures, selecting the narrower temperature range in the system DWR for your application helps the tool to find timing-compliant routing solutions.
Violation Source Clock Destination Clock Slack(ns)
Async
\PWM_1:cy_m0s8_tcpwm_1\/line_out Clock_1
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_SAR_Seq_1_intClock(FFB) ADC_SAR_Seq_1_intClock(FFB) 1.091 MHz 1.091 MHz N/A
Clock_1(FFB) Clock_1(FFB) 12.000 MHz 12.000 MHz N/A
\PWM_1:cy_m0s8_tcpwm_1\/line_out Clock_1(FFB) UNKNOWN UNKNOWN N/A
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz N/A
Clock_1 CyHFCLK 12.000 MHz 12.000 MHz N/A
UART_PC_SCBCLK CyHFCLK 1.412 MHz 1.412 MHz N/A
I2C_1_SCBCLK CyHFCLK 1.600 MHz 1.600 MHz N/A
ADC_SAR_Seq_1_intClock CyHFCLK 1.091 MHz 1.091 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 24.000 MHz 24.000 MHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
I2C_1_SCBCLK(FFB) I2C_1_SCBCLK(FFB) 1.600 MHz 1.600 MHz N/A
UART_PC_SCBCLK(FFB) UART_PC_SCBCLK(FFB) 1.412 MHz 1.412 MHz N/A
+ Asynchronous Clock Crossing Section
+ Source Clock \PWM_1:cy_m0s8_tcpwm_1\/line_out
Source Destination Delay (ns)
Net_991/q cydff_2/main_1 12.658
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(1,1) 1 Net_991 Net_991/clock_0 Net_991/q 1.250
Route 1 Net_991 Net_991/q cydff_2/main_1 2.283
macrocell2 U(1,1) 1 cydff_2 SETUP 3.510
Clock Skew 5.615
\PWM_1:cy_m0s8_tcpwm_1\/line_out cydff_2/main_0 9.078
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,1) 1 \PWM_1:cy_m0s8_tcpwm_1\ Input Delay \PWM_1:cy_m0s8_tcpwm_1\/line_out 0.000
Route 1 Net_968 \PWM_1:cy_m0s8_tcpwm_1\/line_out cydff_2/main_0 5.568
macrocell2 U(1,1) 1 cydff_2 SETUP 3.510
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
cydff_2/q PWM_OUT(0)_PAD 22.707
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(1,1) 1 cydff_2 cydff_2/clock_0 cydff_2/q 1.250
Route 1 cydff_2 cydff_2/q PWM_OUT(0)/pin_input 5.477
iocell8 P0[1] 1 PWM_OUT(0) PWM_OUT(0)/pin_input PWM_OUT(0)/pad_out 15.980
Route 1 PWM_OUT(0)_PAD PWM_OUT(0)/pad_out PWM_OUT(0)_PAD 0.000
Clock Clock path delay 0.000